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Reduced instruction set computer
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11	Everybody be cool, this is a roppery! Vincenzo Iozzo zynamics GmbH Tim Kornau zynamics GmbH Add to Reading List Source URL: www.trailofbits.com Language: English - Date: 2016-04-15 11:36:17 Computing Computer architecture Computer engineering Central processing unit Return-oriented programming Instruction set Processor register Machine code Reduced instruction set computing Gadget Subroutine Stack machine
12	Low-Cost Software Countermeasures Against Fault Attacks: Implementation and Performances Trade Offs Alessandro Barenghi Luca Breveglieri Add to Reading List Source URL: euler.ecs.umass.edu Language: English - Date: 2011-03-24 10:57:36 Computer architecture Computing Computer engineering Central processing unit Computer memory Instruction set architectures Cache Advanced Encryption Standard CPU cache Side-channel attack ARM architecture Reduced instruction set computing
13	A Brief History of RISC, the IBM RS/6000 and the IBM eServer pSeries Reduced Instruction Set Computer (RISC) architecture is the basis for most workstations and UNIX-based servers in use today, and is widely viewed as th Add to Reading List Source URL: sysrun.haifa.il.ibm.com Language: English - Date: 2005-12-19 08:42:34
14	USING INFORMATION THEORY TO STUDY THE EFFICIENCY AND CAPACITY OF COMPUTERS AND SIMILAR DEVICES Boris Ryabko Institute of Computational Technology of Siberian Branch of Russian Academy of Science Siberian State University Add to Reading List Source URL: sp.cs.tut.fi Language: English - Date: 2010-08-12 11:09:05 MMIX Computer MIX Reduced instruction set computing Assembly language Sequence Instruction set Computer architecture Donald Knuth Computing
15	An Overview of Static Pipelining Ian Finlaysony , Gang-Ryung Uhz , David Whalleyy and Gary Tysony y Department of Computer Science z Department of Computer Science Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2011-08-10 14:26:43 Central processing unit Compiler optimizations Instruction set architectures Classes of computers Software pipelining Instruction pipeline MIPS architecture Reduced instruction set computing Transport triggered architecture Computer architecture Computer engineering Computer hardware
16	Improving Low Power Processor Efficiency with Static Pipelining Ian Finlayson† , Gang-Ryung Uh‡ , David Whalley† and Gary Tyson† † ‡ Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2011-01-31 11:18:06 Central processing unit Compiler optimizations Classes of computers Instruction set architectures Software pipelining Instruction pipeline Reduced instruction set computing MIPS architecture Microarchitecture Computer architecture Computing Computer engineering
17	Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers Stephen Hines, David Whalley, Gary Tyson Computer Science Department Florida State University Tallahassee, FL Add to Reading List Source URL: www.cs.fsu.edu Language: English - Date: 2006-08-24 08:01:51 Compiler optimizations Assembly languages Instruction scheduling Reduced instruction set computing Instruction set Branch predication Register renaming Very long instruction word Addressing mode Computer architecture Computing Computer engineering
18	Optimizing for Size: Exploring the Limits of Code Density Vincent M. Weaver ASPLOS XIV Poster Session, 8 MarchAbstract Add to Reading List Source URL: web.eece.maine.edu Language: English - Date: 2009-03-04 12:37:03 X86 Reduced instruction set computing Motorola 68000 family PA-RISC Instruction set Itanium ARM architecture Endianness DEC Alpha Computer architecture Instruction set architectures Very long instruction word
19	The finite state automaton based pipeline hazard recognizer and instruction scheduler in GCC Vladimir N. Makarov Red Hat Add to Reading List Source URL: gcc.cybermirror.org Language: English - Date: 2004-08-29 18:00:00 Central processing unit Classes of computers Parallel computing Models of computation Hazard Superscalar Instruction set Register renaming Reduced instruction set computing Computer architecture Computing Computer engineering
20	J1: a small Forth CPU Core for FPGAs James Bowman Willow Garage Menlo Park, CA Add to Reading List Source URL: excamera.com Language: English - Date: 2010-11-21 15:20:10 Instruction set architectures Central processing unit Stack machine Microcontrollers Instruction set MIPS architecture Reduced instruction set computing MicroBlaze Forth Computer architecture Computing Computer hardware